The present invention relates to a CCD image sensor, and more particularly, to a CCD image sensor which provides improved picture resolution.
CCDs, i.e., charge coupled devices are mainly used for fabricating solid state image sensors or CCD image sensors.
A solid state image sensor is a semiconductor such as silicon onto which a plurality of photodetector and scanner are disposed and can, with a proper photodetector, provide image sensing from the visible region to the infrared region.
As a scanner for solid state image sensor, metal oxide semiconductor (MOS) switches or CCDs have been principally used.
The MOS switch has a problem that it cannot be used for detecting weak signals in which a high signal to noise ratio is required, since the spike noise which occurs during the operation thereof results in a lowering of the signal to noise ratio. Thus, they are hardly used now.
The CCD allows a use of any type of photoconductor as the MOS switch does. In case that the CCD is employed as a scanner, it is preferable to design the CCD part, particularly vertical charge coupled device (hereinafter referred to as a VCCD) in such a way that its surface is as small as possible so that more effective surface of photodetector may be available. This is more important when an interlace manner is adopted, in which a CCD is disposed between photodetectors.
As photodetectors, PN junctions, metal insulator semiconductor (MIS) structures, Schottky junctions and the like are commonly used.
The scanning method using CCDs as a scanner include interlace and non-interlace methods.
In non-interlace method, one frame consists of a plurality of field and the data of input field are scanned to the screen in an order that they are inputted as shown in FIG. 1(a).
The numbers 1, 2, 3 . . . in FIG. 1(a) represent that the scanned fields are displayed according to their input order.
In interlace method, one frame consists of even and odd fields and data of the odd fields and then data of the even fields are scanned to the screen in turn.
In FIG. 1(b), numbers 1 and 2 represent odd and even fields, respectively.
The non-interlace method can acquire the accurate actual image of a moving subject due to rapid scanning speed, so that it may be used for military equipment, for example, missile tracking. Its defect is that the video image is vibrated.
The interlace method can provide a stable video image because the scanning speed is low compared to the non-interlace method. However, a rapidly moving subject is displayed in two images. Therefore, it is not suitable for military equipment but may be used for TV broadcasting of NTSC or PAL signals.
The structure of the above conventional CCD image sensor for interlace method will be described with reference to the accompanying FIG. 2(a) to (e).
Hereinafter, the odd-numbered horizontal line in which photo diodes (PD) are disposed is referred to as an odd horizontal line and the even-numbered horizontal line is referred to as an even horizontal line.
FIG. 2(a) shows a block diagram of a CCD image sensor in the conventional interlace method. Each photo diode (PD) is connected consecutively to a corresponding VCCD region (VCCD) in such a way that output video signal charge may be transferred to VCCD in only one direction while each VCCD region (VCCD) is connected to the HCCD region (HCCD) so that signal charges coming out of each photo diode (PD) may be transferred to HCCD region (HCCD) through the first to fourth VCCD clock signals (V.phi..sub.1 -V.phi..sub.4) consisting of 4 phases.
FIG. 2(b) shows a layout diagram of a CCD image sensor according to a structure of FIG. 2(a). A channel stop region (ST) is formed between VCCD region (VCCD) and photo diode (PD). Odd gate electrode (PG.sub.1) to which the first and second VCCD clock signals (V.phi..sub.1, V.phi..sub.2) are applied is formed from VCCD region (VCCD) to channel stop region (ST) so that said odd gate electrode (PG.sub.1) may be connected to corresponding transfer gate (TG.sub.1) of photo diode (PD) disposed in the odd horizontal line while even gate electrode (PG.sub.2) to which the third and fourth VCCD clock signals (V.phi..sub.3 -V.phi..sub.4) are applied, are formed from channel stop region (ST), VCCD region (VCCD) to photo diode (PD) so that said even gate electrode (PG.sub.2) may be connected to corresponding transfer gate (TG.sub.2) of photo diode (PD) disposed in the even horizontal line.
The desired numbers of the odd gate (PG.sub.1) and even gate (PG.sub.2) may be formed consecutively in the same form. They are separated from each other by an insulating material which is not shown.
As a material for transfer gates (TG.sub.1, TG.sub.2), and odd and even gate electrodes (PG.sub.1, PG.sub.2), poly silicon was used.
The odd gate electrode (PG.sub.1) consists of the first odd gate electrode (PG.sub.1a) which is formed under the photo diode (PD) in the odd horizontal line and to which the second VCCD clock signal (V.phi..sub.2) is applied and the second odd gate electrode (PG.sub.1b) which is formed in the upper region of the photo diode (PD) in the odd horizontal line, to which the first VCCD clock signal (V.phi..sub.1) is applied and which is connected to the transfer gate (TG.sub.1) of the photo diode (PD) formed in the odd horizontal line.
The even gate electrode (PG.sub.2) consists of the first even gate electrode (PG.sub.2a) which is formed under the photo diode (PD) in the even horizontal line and to which the fourth VCCD clock signal (V.phi..sub.4) is applied and the second even gate electrode (PG.sub.2b) which is formed in the upper region of the photo diode (PD) in the even horizontal line, to which the third VCCD clock signal (V.phi..sub.3) is applied and which is connected to the transfer gate (TG.sub.2) of the photo diode (PD) formed in the even horizontal line.
The first to fourth VCCD clock signals (V.phi..sub.1 -V.phi..sub.4), which are of four phases, consist of even and odd fields. The clocking of the VCCD will be hereinafter described in more detail.
FIG. 2(c) shows a cross sectional view taken along the a--a' line of FIG. 2(b). A p-type well 200 is formed on the n-type substrate (100). An n-type photo diode (PD) and n-type VCCD region (VCCD), which are formed in the even horizontal line, are disposed consecutively apart from each other by the width of a channel stop region (ST). A transfer gate (TG.sub.2) for connecting the photo diode (PD) and the VCCD region (VCCD) is formed in the upper region of the space by which the photo diode (PD) and the VCCD region (VCCD) are separated from each other and, in the upper region of surface of the VCCD region (VCCD), the second even gate electrode (PG.sub.2b) of even gate electrode (PG.sub.2), to which the third VCCD clock signal (V.phi..sub.3) is applied, is connected to the corresponding transfer gate (TG.sub.2) of the photo diode (PD) in even horizontal line.
The p-type well 200 consists of shallow (200a) and deep (200b) p-type wells in order to control the over flow drain (OFD) voltage.
On the surface of photo diode (PD), a p.sup.+ -type thin film 300 is usually formed to apply the initial vias. The figure P.sup.+ under the channel stop region (ST) represents channel stop ion.
FIG. 2(d) shows a cross sectional view taken along the c--c' line of FIG. 2(b). In FIG. 2(d), a p-type well 200 is formed on an n-type substrate 100, and n-type photo diode (PD) and n-type VCCD region (VCCD) in the even horizontal line are disposed consecutively apart from each other by a distance of channel stop region and the first even gate electrode (PG.sub.2a) of the even gate electrode (PG.sub.2) to which the fourth VCCD clock signal (V.phi..sub.4) is applied, is formed in the upper region of the surface of the VCCD region (VCCD).
In FIG. 2(d), like FIG. 2(c), conventional p.sup.+ -type thin film 300 is formed on the surface of photo diode (PD) and the figure p.sup.+ shown under the channel stop region (ST) represents p.sup.+ -type ion for a channel stop region. The p-type well 200 consists of shallow (200a) and deep (200b) p-type wells In order to control the OFD voltage.
Accordingly, the transfer gate (TG.sub.1) of the photo diode (PD) formed in the odd horizontal line can be driven only by the first VCCD clock signal (V.phi..sub.1) which is applied to the second odd gate electrode (PG.sub.1b) of the odd gate electrode (PG.sub.1). Further, the transfer gate (TG.sub.2) of the photo diode (PD) formed in the even horizontal line can be driven only by the third VCCD clock signal (V.phi..sub.3) which is applied to the second even gate electrode (PG.sub.2b) of the even gate electrode (PG.sub.2).
The second VCCD clock signal (V.phi..sub.2) which is applied to the first odd gate electrode (PG.sub.1a) of the odd gate electrode (PG,) and the fourth VCCD clock signal (V.phi..sub.4) which is applied to the first even gate electrode (PG.sub.2a) of the even gate electrode (PG.sub.2) have a function of shifting the image signal charge coming out of the photo diodes (PD) formed in the odd and even horizontal lines to a HCCD (Horizontal Charge Coupled Device).
Hereinafter, operation of the conventional CCD image sensor will be described with reference to the accompanying FIG. 3(a) which shows a timing diagram of the first to fourth VCCD clock signals (V.phi..sub.1 -V.phi..sub.4) which are of 4 phases.
Each clock signal consists of two fields, i.e., one odd field and one even field.
In the odd field, a transfer gate driving voltage (V.sub.1) of high level state (15V) is involved in the first VCCD clock signal (V.phi..sub.1) which is applied to the second odd gate electrode (PG.sub.1b) of the odd gate electrode (PG.sub.1).
In the even field, a transfer gate driving voltage (V.sub.2) of high level state (15V) is involved in the third VCCD clock signal (V.phi..sub.3) which is applied to the second even gate electrode (PG.sub.2b) of the even gate electrode (PGs).
First, when in the odd field, the first to fourth VCCD clock signals (V.phi..sub.1 -V.phi..sub.4) are applied simultaneously, the transfer gates (TG.sub.1) of the photo diodes (PD) formed in each odd horizontal line are turned on simultaneously by the transfer gate driving voltage (V.sub.1) involved in the first VCCD clock signal (V.phi..sub.1).
Accordingly, an image signal charge generated at the photo diode (PD) is transferred to the VCCD region from which it is moved again to the HCCD region by the clocking operating of VCCD.
FIG. 3(b) shows a pulse waveform diagram of the applied first to fourth clock signals (V.phi..sub.1 -V.phi..sub.4) in the unit section (K) of FIG. 3(a).
The image signal charge coming out of the photo diode (PD) by serial clocking operations as shown in FIG. 3(b) is moved in a vertical direction to the HCCD region (HCCD).
The second VCCD clock signal (V.phi..sub.2) which is applied through the first odd gate electrode (PG.sub.1a) of the odd gate electrode (PG.sub.1) formed under the odd horizontal line has a function of shifting the image signal charge coming out of the photo diode (PD) in the odd horizontal line by said first VCCD clock signal (V.phi..sub.1) to the HCCD region (HCCD) by aid of said first VCCD clock signal (V.phi..sub.1).
In the even field of FIG. 3(a), when the first to fourth clock signals (V.phi..sub.1 -V.phi..sub.4) are applied simultaneously, the transfer gates (TG.sub.2) of the photo diodes (PD) formed in each even horizontal line are turned on by the transfer gate driving voltage (V.sub.2) involved in the third VCCD clock signal (V.phi..sub.3).
Accordingly, an image signal charge generated at the photo diode (PD) in the even horizontal line is moved in a vertical direction to the HCCD region by the clocking operation, like in FIG. 3(b) for odd fields.
The fourth VCCD clock signal (VO.phi..sub.4) which is applied through the first even gate electrode (PG.sub.2a) of the even gate electrode (PG.sub.2) formed under the even horizontal line has a function of, together with the third VCCD clock signal (V.phi..sub.3), shifting the image signal charge coming out of the photo diode (PD) in the even horizontal line by said third VCCD clock signal (V.phi..sub.3).
Use of VCCD clock signals of 4 phases makes it possible to transfer more image signal charge than if VCCD clock signals of 2 phases were used.
According to the above description of operation, first, the image signal charges of the photo diodes (PD) disposed in the odd horizontal line are scanned to the screen in due turn by the first to fourth VCCD clock signals (V.phi..sub.1 -V.phi..sub.4) which are of 4 Phases through the VCCD region (VCCD) and HCCD region (HCCD). Then, the image signal charges of the photo diodes (PD) disposed in the even horizontal lines are scanned to the screen in due turn through the VCCD region (VCCD) and HCCD region (HCCD).
The above explained scanning method is called the interlace method.
As shown in FIG. 2(a), when the signal charge of the photo diodes (PD) disposed in the odd horizontal line, referred to as 1, and the signal charge of the photo diode (PD) disposed in the even horizontal line, referred to as 2, a state of the screen (the frame) consisting of pixels which are displayed by said image signal charges 1 and 2 may be shown as FIG. 3(c).
However, such a CCD image sensor of the prior art has problems that, although said CCD image sensor using the interlace method is widely used for TV broadcasting of NTSC or PAL signals, the VCCD region, which does not participate in receiving the image signal, is too broad in view of the total chip surface of said CCD image sensor since the VCCD is disposed between photodetectors. Consequently, it is hard to obtain a high resolution video due to restriction in increasing the photodetectors for improving resolution with defined chip size.